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| INTEGRATED CIRCUITS DATA SHEET TDA8004AT IC card interface Preliminary specification File under Integrated Circuits, IC02 2000 Feb 29 Philips Semiconductors Preliminary specification IC card interface FEATURES * 3 or 5 V supply for the IC (GND and VDD) * Step-up converter for VCC generation (separately powered with a 5 V 10% supply, VDDP and PGND) * 3 specific protected half duplex bidirectional buffered I/O lines (C4, C7 and C8) * VCC regulation (5 or 3 V 5% on 2 x 100 nF or 1 x 100 nF and 1 x 220 nF multilayer ceramic capacitors with low ESR, ICC < 65 mA at 4.5 V < VDDP < 6.5 V, current spikes of 40 nAs up to 20 MHz, with controlled rise and fall times, filtered overload detection approximately 90 mA) * Thermal and short-circuit protections on all card contacts * Automatic activation and deactivation sequences (initiated by software or by hardware in the event of a short-circuit, card take-off, overheating or supply drop-out) * Enhanced ESD protection on card side (>6 kV) * 26 MHz integrated crystal oscillator * Clock generation for the card up to 20 MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals) with synchronous frequency changes * Non-inverted control of RST via pin RSTIN * ISO 7816, GSM11.11 and EMV (payment systems) compatibility * Supply supervisor for spikes killing during power-on and power-off * One multiplexed status signal OFF. ORDERING INFORMATION TYPE NUMBER TDA8004AT PACKAGE NAME SO28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm APPLICATIONS * IC card readers for banking * Electronic payment * Identification * Pay TV. GENERAL DESCRIPTION TDA8004AT The TDA8004AT is a complete low cost analog interface for asynchronous 3 or 5 V smart cards. It can be placed between the card and the microcontroller with very few external components to perform all supply protection and control functions. VERSION SOT136-1 2000 Feb 29 2 Philips Semiconductors Preliminary specification IC card interface QUICK REFERENCE DATA SYMBOL Supplies VDD VDDP IDD supply voltage step-up supply voltage supply current inactive mode; VDD = 3.3 V; fXTAL = 10 MHz active mode; VDD = 3.3 V; fXTAL = 10 MHz; no load IDDP step-up supply current inactive mode; VDDP = 5 V; fXTAL = 10 MHz active mode; VDDP = 5 V; fXTAL = 10 MHz; no load Card supply VCC card supply voltage including ripple 5 V card DC ICC < 65 mA AC current spikes of 40 nAs 3 V card DC ICC < 65 mA AC current spikes of 40 nAs Vi(ripple)(p-p) ripple voltage on VCC (peak-to-peak value) ICC General fCLK tde Ptot Tamb card clock frequency deactivation cycle duration continuous total power dissipation ambient temperature Tamb = -25 to +85 C 0 60 - -25 - 80 - - card supply current from 20 kHz to 200 MHz VCC from 0 to 5 or to 3 V 2.85 2.76 - - - - - - 4.75 4.65 - - 2.7 4.5 - - - - - 5 - - - - PARAMETER CONDITIONS MIN. TDA8004AT TYP. MAX. UNIT 6.5 6.5 1.2 1.5 0.1 18 V V mA mA mA mA 5.25 5.25 3.15 3.20 350 65 V V V V mV mA 20 100 0.56 +85 MHz s W C 2000 Feb 29 3 Philips Semiconductors Preliminary specification IC card interface BLOCK DIAGRAM TDA8004AT VDD 100 nF handbook, full pagewidth VDDP 100 nF 100 nF S1 7 S2 5 4 PGND STEP-UP CONVERTER INTERNAL REFERENCE Vref INTERNAL OSCILLATOR 2.5 MHz 8 VUP 100 nF 21 SUPPLY 6 VOLTAGE SENSE ALARM EN1 CLKUP OFF RSTIN CMDVCC 5V/3V 23 20 19 3 SEQUENCER EN2 PVCC VCC GENERATOR 17 VCC 14 CGND 100 nF 100 nF EN5 RST BUFFER 16 RST CLKDIV1 CLKDIV2 1 2 CLOCK CIRCUITRY HORSEQ EN4 CLOCK BUFFER 15 10 9 CLK PRES PRES CLK EN3 OSCILLATOR THERMAL PROTECTION XTAL1 XTAL2 24 25 AUX1UC 27 I/O TRANSCEIVER 13 AUX1 TDA8004AT AUX2UC 28 I/O TRANSCEIVER 12 AUX2 I/OUC 26 I/O TRANSCEIVER 11 I/O 22 GND 18 n.c. FCE658 All capacitors are mandatory. Fig.1 Block diagram. 2000 Feb 29 4 Philips Semiconductors Preliminary specification IC card interface PINNING SYMBOL CLKDIV1 CLKDIV2 5V/3V PGND S2 VDDP S1 VUP PRES PRES I/O AUX2 AUX1 CGND CLK RST VCC n.c. CMDVCC RSTIN VDD GND OFF XTAL1 XTAL2 I/OUC AUX1UC AUX2UC PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I I I supply I/O supply I/O O I I I/O I/O I/O supply O O O - I I supply supply O I O I/O I/O I/O DESCRIPTION control with CLKDIV2 for choosing CLK frequency control with CLKDIV1 for choosing CLK frequency control signal for selecting VCC = 5 V (HIGH) or VCC = 3 V (LOW) power ground for step-up converter TDA8004AT capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 m must be connected between pins S1 and S2) power supply voltage for step-up converter capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 m must be connected between pins S1 and S2) output of step-up converter (a 100 nF capacitor with ESR < 100 m must be connected to PGND) card presence contact input (active LOW); if PRES or PRES is true, then the card is considered as present card presence contact input (active HIGH); if PRES or PRES is true, then the card is considered as present data line to and from card (C7) (internal 10 k pull-up resistor connected to VCC) auxiliary line to and from card (C8) (internal 10 k pull-up resistor connected to VCC) auxiliary line to and from card (C4) (internal 10 k pull-up resistor connected to VCC) ground for card signals clock to card (C3) card reset (C2) supply for card (C1); decouple to CGND with 2 x 100 nF or 1 x 100nF and 1 x 220 nF capacitors with ESR < 100 m (with 220 nF, the noise margin on VCC will be higher) not connected start activation sequence input from microcontroller (active LOW) card reset input from microcontroller (active HIGH) supply voltage ground NMOS interrupt to microcontroller (active LOW) with 20 k internal pull-up resistor connected to VDD (refer section "Fault detection") crystal connection or input for external clock crystal connection (leave open circuit if an external clock source is used) microcontroller data I/O line (internal 10 k pull-up resistor connected to VDD) auxiliary line to and from microcontroller (internal 10 k pull-up resistor connected to VDD) auxiliary line to and from microcontroller (internal 10 k pull-up resistor connected to VDD) 2000 Feb 29 5 Philips Semiconductors Preliminary specification IC card interface FUNCTIONAL DESCRIPTION TDA8004AT Throughout this document, it is assumed that the reader is familiar with ISO7816 norm terminology. Power supply The supply pins for the IC are VDD and GND. VDD should be in the range from 2.7 to 6.5 V. All interface signals with the microcontroller are referenced to VDD; therefore be sure the supply voltage of the microcontroller is also at VDD. All card contacts remain inactive during powering up or powering down. The sequencer is not activated until VDD reaches Vth2 + Vhys(th2) (see Fig.3). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. For generating a 5 V 5% VCC supply to the card, an integrated voltage doubler is incorporated. This step-up converter should be separately supplied by VDDP and PGND (from 4.5 to 6.5 V). Due to large transient currents, the 2 x 100 nF capacitors of the step-up converter should have an ESR of less than 100 m, and be located as near as possible to the IC. The supply voltages VDD and VDDP may be applied to the IC in any time sequence. If a voltage between 7 and 9 V is available within the application, this voltage may be tied to pin VUP, thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor between pins S1 and S2 may be omitted. Voltage supervisor This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.3)). As long as VDD is less than Vth2 + Vhys(th2), the IC will remain inactive whatever the levels on the command lines. This also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys(th2). Fig.2 Pin configuration. The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth2, a deactivation sequence of the contacts is performed. handbook, halfpage CLKDIV1 1 CLKDIV2 2 5V/3V 3 PGND 4 S2 5 VDDP 6 S1 7 28 AUX2UC 27 AUX1UC 26 I/OUC 25 XTAL2 24 XTAL1 23 OFF 22 GND TDA8004AT VUP 8 PRES 9 PRES 10 I/O 11 AUX2 12 AUX1 13 CGND 14 FCE659 21 VDD 20 RSTIN 19 CMDVCC 18 n.c. 17 VCC 16 RST 15 CLK 2000 Feb 29 6 Philips Semiconductors Preliminary specification IC card interface TDA8004AT handbook, full pagewidth VDD Vth2 + Vhys(th2) Vth2 tW tW ALARM (internal signal) FCE660 Fig.3 Alarm as a function of VDD (tW = 10 ms). Clock circuitry The clock signal (CLK) to the card is either derived from a clock signal input on pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The frequency may be chosen at fXTAL, 12fXTAL, 14fXTAL or 18fXTAL via pins CLKDIV1 and CLKDIV2. The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. In the case of fXTAL, the duty factors are dependent on the signal at XTAL1. In order to reach a 45% to 55% duty factor on pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period. If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence (see Fig.5). If the signal applied to XTAL1 is controlled by the microcontroller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. Table 1 Clock circuitry definition CLKDIV2 0 1 1 0 CLK 1 1 1 8fXTAL 4fXTAL 2fXTAL CLKDIV1 0 0 1 1 fXTAL 2000 Feb 29 7 Philips Semiconductors Preliminary specification IC card interface I/O circuitry The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data lines I/O and I/OUC being pulled HIGH via a 10 k resistor (I/O to VCC and I/OUC to VDD). I/O is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC VDD. The first line on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which then becomes the slave. After a time delay td(edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus transmitting the logic 0 present on the master line. When the master line returns to logic 1, the P transistor on the slave line is turned on during the time delay td(edge) and then both lines return to their Idle states. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9VCC on a 80 pF load. At the end of the active pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the load current (see Fig.4). The maximum frequency on these lines is 1 MHz. Inactive state TDA8004AT After power-on reset, the circuit enters the inactive state. A minimum number of circuits are active while waiting for the microcontroller to start a session. * All card contacts are inactive (approximately 200 to GND) * I/OUC, AUX1UC and AUX2UC are high impedance (10 k pull-up resistor connected to VDD) * Voltage generators are stopped * XTAL oscillator is running * Voltage supervisor is active. Activation sequence After power-on and, after the internal pulse width delay, the microcontroller may check the presence of the card with the signal OFF (OFF = HIGH while CMDVCC is HIGH means that the card is present; OFF = LOW while CMDVCC is HIGH means that no card is present). If the card is in the reader (which is the case if PRES or PRES is true), the microcontroller may start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.5): * CMDVCC is pulled LOW (t0) * The voltage doubler is started (t1 ~ t0) * VCC rises from 0 to 5 or 3V with a controlled slope (t2 = t1 + 123T) (I/O, AUX1 and AUX2 follow VCC with a slight delay); T is 64 times the period of the internal oscillator, approximately 25s * I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) * CLK is applied to the C3 contact (t4) * RST is enabled (t5 = t1 + 7T). The clock may be applied to the card in the following way: Set RSTIN HIGH before setting CMDVCC LOW, and reset it LOW between t3 and t5; CLK will start at this moment. RST will remain LOW until t5, where RST is enabled to be the copy of RSTIN. After t5, RSTIN has no further action on CLK. This is to allow a precise count of CLK pulses before toggling RST. If this feature is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3, and after t5, RSTIN may be set HIGH in order to get the Answer To Request (ATR) from the card. handbook, halfpage 6 FCE661 12 Io (mA) Vo (V) (1) (2) 4 8 2 4 0 0 20 40 t (ns) 0 60 (1) Current. (2) Voltage. Fig.4 I/O, AUX1 and AUX2 output voltage and current as a function of time during a LOW-to-HIGH transition. 2000 Feb 29 8 Philips Semiconductors Preliminary specification IC card interface TDA8004AT handbook, full pagewidth tact OSC_INT/64 CMDVCC VUP VCC I/O CLK RSTIN RST t0 FCE662 t1 t2 ATR high - Z t3 t4 t5 Fig.5 Activation sequence. Active state When the activation sequence is completed, the TDA8004AT will be in the active state. Data is exchanged between the card and the microcontroller via the I/O lines. The TDA8004AT is designed for cards without VPP (this is the voltage required to program or erase the internal non-volatile memory). Depending on the layout and on the application test conditions (for example with an additional 1 pF cross capacitance between C2/C3 and C2/C7) it is possible that C2 is polluted with high frequency noise from C3. In this case, it will be necessary to connect a 220 pF capacitor between C2 and CGND. It is recommended to: 1. Keep track C3 as far as possible from other tracks 2. Have straight connection between CGND and C5 (the 2 capacitors on C1 should be connected to this ground track) 3. Avoid ground loops between CGND, PGND and GND 4. Decouple VDDP and VDD separately; if the 2 supplies are the same in the application, then they should be connected in star on the main track. With all these layout precautions, noise should be at an acceptable level, and jitter on C3 should be less than 100 ps. Refer to Application Note AN97036 for specimen layouts. Deactivation sequence When a session is completed, the microcontroller sets the CMDVCC line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Fig.6): * RST goes LOW (t11 = t10) * CLK is stopped LOW (t12 = t11 + 12T); where T is approximately 25 s * I/O, AUX1 and AUX2 are output into high-impedance state (t13 = t11 + T) (10 k pull-up resistor connected to VCC) * VCC falls to zero (t14 = t11 + 123T); the deactivation sequence is completed when VCC reaches its inactive state * VUP falls to zero (t15 = t11 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain pulled up to VDD via a 10 k resistor. 2000 Feb 29 9 Philips Semiconductors Preliminary specification IC card interface TDA8004AT handbook, full pagewidth tde OSC_INT/64 t10 t15 VUP t14 VCC t13 I/O t12 CLK RST high - Z CMDVCC t11 FCE663 Fig.6 Deactivation sequence. Fault detection The following fault conditions are monitored by the circuit: * Short-circuit or high current on VCC * Removing card during transaction * VDD dropping * Overheating. There are two different cases ((see Fig.7)) 1. CMDVCC HIGH: (outside a card session) then, OFF is LOW if the card is not in the reader, and HIGH if the card is in the reader. A supply voltage drop on VDD is detected by the supply supervisor which generates an internal power-on reset pulse, but does not act upon OFF. The card is not powered-up, so no short-circuit or overheating is detected. 2. CMDVCC LOW: (within a card session) then, OFF falls LOW if the card is extracted, or if a short-circuit has occurred on VCC, or if the temperature on the IC has become too high. As soon as the fault is detected, an emergency deactivation is automatically performed (see Fig.8). When the system controller sets CMDVCC back to HIGH, it may sense OFF again in order to distinguish between a hardware problem or a card extraction. If a supply voltage drop on VDD is detected whilst the card is activated, then an emergency deactivation will be performed, but OFF remains HIGH. Depending on the type of card presence switch within the connector (normally closed or normally open), and on the mechanical characteristics of the switch, a bouncing may occur on presence signals at card insertion or withdrawal. There is no debounce feature in the device, so the software has to take it into account; however, the detection of card take off during active phase, which initiates an automatic deactivation sequence is done on the first True/ False transition on PRES or PRES, and is memorized until the system controller sets CMDVCC HIGH. So, the software may take some time waiting for presence switches to be stabilized without causing any delay on the necessary fast and normalized deactivation sequence. 2000 Feb 29 10 Philips Semiconductors Preliminary specification IC card interface TDA8004AT handbook, full pagewidth PRES OFF CMDVCC VCC Deactivation caused by cards withdrawal Deactivation caused by short circuit FCE665 Fig.7 Behaviour of OFF, CMDVCC, PRES and VCC (see also application note AN97036 for software decision algorithm on OFF signal). handbook, full pagewidth tde OSC_INT/64 t10 OFF PRES t14 VCC t13 I/O t12 CLK RST t11 FCE664 high - Z Fig.8 Emergency deactivation sequence. VCC regulator The VCC buffer is able to deliver up to 65 mA continuously (at 5V if 5V/3V is HIGH or 3 V if 5V/3V is LOW). It has an internal overload detection at approximately 90 mA. This detection is internally filtered, allowing spurious current pulses up to 200 mA to be drawn by the card without causing a deactivation (the average current value must stay below 65 mA). For VCC accuracy reasons, a 100 nF capacitor with an ESR < 100 m should be tied to CGND near pin 17, and a 100 nF (or better 220 nF) with same ESR should be tied to CGND near to the C1 contact. 2000 Feb 29 11 Philips Semiconductors Preliminary specification IC card interface LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL VDD, VDDP Vn1 supply voltage voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, CMDVCC and OFF voltage on card contact pins PRES, PRES, I/O, RST, AUX1, AUX2 and CLK voltage on pins VUP, S1 and S2 IC storage temperature continuous total power dissipation junction temperature electrostatic voltage on pins I/O, RST, VCC, AUX1, CLK, AUX2, PRES and PRES electrostatic voltage on all other pins Tamb = -25 to +85 C PARAMETER CONDITIONS TDA8004AT MIN. -0.3 -0.3 MAX. +7 +7 UNIT V V Vn2 Vn3 Tstg Ptot Tj Ves1 Ves2 Notes -0.3 - -55 - - -6 -2 +7 +9 +125 0.56 150 +6 +2 V V C W C kV kV 1. All card contacts are protected against any short with any other card contact. 2. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional operation of the device under this condition is not implied. HANDLING Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM; 1500 ; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground. THERMAL RESISTANCE SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 70 UNIT K/W 2000 Feb 29 12 Philips Semiconductors Preliminary specification IC card interface TDA8004AT CHARACTERISTICS VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; all parameters remain within limits but are only statistically tested for the temperature range; fXTAL = 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a parameter is specified as a function of VDD or VCC it means their actual value at the moment of measurement. SYMBOL Temperature Tamb Supplies VDD VDDP Vo(VUP) Vi(VUP) supply voltage supply voltage for the voltage doubler output voltage on pin VUP from step-up converter input voltage to be applied on VUP in order to block the step-up converter supply current inactive mode active mode; fCLK = fXTAL; CL = 30 pF IP supply current for the step-up converter inactive mode active mode; ICC = 0; fCLK = fXTAL; CL = 30 pF ICC = 0 ICC = 65 mA Vth2 Vhys(th2) tW VCC threshold voltage on VDD (falling) hysteresis on Vth2 width of the internal ALARM pulse - - 2.2 50 6 - 0.1 - 0.1 - - - - - - - 18 150 2.4 150 20 mA mA V mV ms 2.7 4.5 - 7 - 5 5.5 - 6.5 6.5 - 9 V V V V ambient temperature -25 - +85 C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDD - - - - - - 1.2 1.5 0.1 mA mA mA Card supply voltage; note 1 output voltage including ripple inactive mode inactive mode; ICC = 1 mA active mode; ICC < 65 mA DC 5 V card 3 V card active mode; single current pulse of -100 mA; 2 s 5 V card 3 V card active mode; current pulses of 40 nAs with ICC < 200 mA; t < 400 ns 5 V card 3 V card Vi(ripple)(p-p) 2000 Feb 29 peak-to-peak ripple voltage on VCC from 20 kHz to 200 MHz 13 4.65 2.76 - - - - 5.25 3.20 350 V V mV 4.65 2.76 - - 5.25 3.15 V V 4.65 2.85 - - 5.25 3.15 V V +0.1 +0.4 V V Philips Semiconductors Preliminary specification IC card interface TDA8004AT SYMBOL ICC SR PARAMETER output current slew rate CONDITIONS from 0 to 5 or 3 V VCC short-circuit to ground up and down - - MIN. TYP. - - 0.17 - - - - MAX. 65 120 0.22 UNIT mA mA V/s 0.11 Crystal connections (pins XTAL1 and XTAL2) Cext fi(XTAL) VIH(XTAL) VIL(XTAL) external capacitors on pins XTAL1 and XTAL2 crystal input frequency HIGH-level input voltage on XTAL1 LOW-level input voltage on XTAL1 depending on specification - of crystal or resonator used 2 0.8VDD -0.3 15 26 +0.2VDD pF MHz V VDD + 0.2 V Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC) GENERAL td(edge) delay between falling edge on pins I/OUC and I/O (or I/O and I/OUC) and width of active pull-up pulse maximum frequency on data lines input capacitance on data lines - 200 - ns fI/O(max) Ci VOH VOL VIH VIL Vinactive Iedge ILIH IIL tt(DI) tt(DO) - - no DC load IOH = -40 A I = 1 mA 0.9VCC 0.75VCC - 1.8 -0.3 no load II/O = 1 mA VOH = 0.9VCC ; Co = 80 pF VIH = VCC VIL = 0 V from VIL max to VIH min Co = 80 pF, no DC load; 10% to 90% from 0 to VCC (see Fig.9) - - -1 - - - - - - - - - - - - - - - - - - 1 10 MHz pF DATA LINES; PINS I/O, AUX1 AND AUX2 (WITH 10 K PULL-UP RESISTOR CONNECTED TO VCC) HIGH-level output voltage on data lines LOW-level output voltage on data lines HIGH-level input voltage on data lines LOW-level input voltage on data lines voltage on data lines outside a session current from data lines when active pull-up active input leakage current HIGH on data lines LOW-level input current on data lines input transition times on data lines output transition times on data lines VCC + 0.1 V VCC + 0.1 V 300 mV VCC + 0.3 V +0.8 0.1 0.3 - 10 600 1 0.1 V V V mA A A s s DATA LINES; PINS I/OUC, AUX1UC AND AUX2UC (WITH 10 K PULL-UP RESISTOR CONNECTED TO VDD) VOH VOL HIGH-level output voltage on data lines LOW-level output voltage on data lines no DC load IOH = -40 A I = 1 mA 0.9VDD 0.75VDD - - - - VDD + 0.2 V VDD + 0.2 V 300 mV 2000 Feb 29 14 Philips Semiconductors Preliminary specification IC card interface TDA8004AT SYMBOL VIH VIL ILIH IIL Rpu(int) tt(DI) tt(DO) PARAMETER HIGH-level input voltage on data lines LOW-level input voltage on data lines input leakage current HIGH on data lines LOW-level input on data lines internal pull-up resistance between data lines and VDD input transition times on data lines output transition times on data lines CONDITIONS MIN. 0.7VDD 0 TYP. - - - - 11 - - MAX. UNIT VDD + 0.3 V 0.3VDD 10 600 13 1 0.1 V A A k s s VIH = VDD VIL = 0 V - - 9 from VIL max to VIH min Co = 30 pF; 10% to 90% from 0 to VDD (see Fig.9) - - Internal oscillator fosc(int) Vo(inactive) frequency of internal oscillator 2.2 - - - - - - - - - - - - - - - - - - - - 135 - 3.2 MHz Reset output to the card (pin RST) output voltage in inactive mode no load Io = 1 mA td(RSTIN-RST) delay between pins RSTIN and RST RST enabled VOL VOH tr, tf Vo(inactive) VOL VOH tr, tf SR LOW-level output voltage HIGH-level output voltage rise and fall times IOL = 200 A IOH = -200 A Co = 250 pF no load Io = 1 mA LOW-level output voltage HIGH-level output voltage rise and fall times duty factor (except for fXTAL) slew rate (rise and fall) IOL = 200 A IOH = -200 A CL = 35 pF; note 2 CL = 35 pF; note 2 CL = 35 pF 0 0 - 0 0.9VCC - 0 0 0 0.9VCC - 45 0.2 - 0.7VDD 0 < VIL < VDD 0 < VIH < VDD - - - 0.75VDD - - 0.1 0.3 2 0.3 VCC 0.1 V V s V V s V V V V ns % V/ns Clock output to the card (pin CLK) output voltage in inactive mode 0.1 0.3 0.3 VCC 8 55 - 0.3VDD - 5 5 Logic inputs (pins CLKDIV, CLKDIV2,PRES, PRES, CMDVCC, RSTIN and 5V/3V); note 3 VIL VIH ILIL ILIH LOW-level input voltage HIGH-level input voltage input leakage current LOW input leakage current HIGH V V A A OFF output (pin OFF is an open-drain with an internal 20 k pull-up resistor to VDD) VOL VOH Protections Tsd ICC(sd) shut-down temperature shut-down current at VCC - 110 C mA LOW-level output voltage HIGH-level output voltage IOL = 2 mA IOH = -15 A 0.4 - V V 2000 Feb 29 15 Philips Semiconductors Preliminary specification IC card interface TDA8004AT SYMBOL Timing tact tde t3 t5 Notes PARAMETER CONDITIONS - 60 - MIN. TYP. MAX. UNIT s s s s activation sequence duration deactivation sequence duration start of the window for sending CLK to the card end of the window for sending CLK to the card see Fig.5 see Fig.6 see Fig.5 see Fig.5 180 80 - - 220 100 130 - 140 1. To meet these specifications VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 100 nF and one 220 nF. t1 2. The transition times and duty factor definitions are shown in Fig.9; = -------------t1 + t2 3. PRES and CMDCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1. handbook, full pagewidth tr 90% tf 90% VOH (VOH + VOL)/2 10% t1 10% t2 VOL FCE666 Fig.9 Definition of output transition times. 2000 Feb 29 16 Philips Semiconductors Preliminary specification IC card interface APPLICATION DIAGRAM TDA8004AT handbook, full pagewidth More application information on application report AN97036 VDD for the TDA8004 must be the same as controller supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES, PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC, OFF should be referenced to VDD, and also XTAL1 if driven by external clock. 100 nF +5 V 10 F CLKDIV1 CLKDIV2 5V/3V GNDP S2 1 2 3 4 5 6 7 28 27 26 25 24 23 22 AUX2UC AUX1UC I/OUC XTAL2 XTAL1 OFF GND VDD RSTIN CMDVCC n.c. VCC RST CLK +3.3 V 100 nF +3.3 V 33 pF 3.3 V POWERED MICROCONTROLLER 100 nF VDDP S1 VUP TDA8004AT 8 9 10 11 12 13 14 21 20 19 18 17 16 15 100 nF 100 nF PRES PRES These capacitors must be placed near the IC and have LOW ESR (Less than 1 cm) +3.3 V 100 k I/O AUX2 AUX1 CGND Straight and short connextions between CGND, C5 and capacitors GND. (No loop) One 100nF with LOW ESR near pin 17, One 100nF or 220nF with LOW ESR near C1 contact (less than 1cm) C3 should be routed far from C2, C7, C4 and C8 and, better, surrounded with ground tracks. CARD READ (Normally closed type) 220 nF C5 C6 C7 C8 C1 C2 C3 C4 K1 K2 FCE667 Fig.10 Application diagram. 2000 Feb 29 17 Philips Semiconductors Preliminary specification IC card interface PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm TDA8004AT SOT136-1 D E A X c y HE vMA Z 28 15 Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.9 0.4 0.035 0.016 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 2000 Feb 29 18 Philips Semiconductors Preliminary specification IC card interface SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: TDA8004AT * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Feb 29 19 Philips Semiconductors Preliminary specification IC card interface Suitability of surface mount IC packages for wave and reflow soldering methods TDA8004AT SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Short-form specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2000 Feb 29 20 Philips Semiconductors Preliminary specification IC card interface NOTES TDA8004AT 2000 Feb 29 21 Philips Semiconductors Preliminary specification IC card interface NOTES TDA8004AT 2000 Feb 29 22 Philips Semiconductors Preliminary specification IC card interface NOTES TDA8004AT 2000 Feb 29 23 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 69 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/01/pp24 Date of release: 2000 Feb 29 Document order number: 9397 750 06685 |
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